1997-09-22 - FPGAs

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From: ghio@temp0115.myriad.ml.org (Matthew Ghio)
To: cypherpunks@cyberpass.net
Message Hash: 93d8ffe81f7b42e84e0ae4d1aa003e1ea9387e6db57479fc2792398cf5491e66
Message ID: <199709220314.XAA14274@myriad>
Reply To: N/A
UTC Datetime: 1997-09-22 03:20:37 UTC
Raw Date: Mon, 22 Sep 1997 11:20:37 +0800

Raw message

From: ghio@temp0115.myriad.ml.org (Matthew Ghio)
Date: Mon, 22 Sep 1997 11:20:37 +0800
To: cypherpunks@cyberpass.net
Subject: FPGAs
Message-ID: <199709220314.XAA14274@myriad>
MIME-Version: 1.0
Content-Type: text/plain



Here are a few programs which haven't been mentioned here before.  They take
C/C++ code and compile it to FPGAs, which might be interesting to someone
who's working on, oh, say RC5...

The first is at http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmcc/
and compiles C code to Xilinx or Altera FPGAs.

Another is at ftp://lslsun5.epfl.ch/pub/nlc*
It uses a slightly different syntax and targets Xilinx chips.

There's also a routing optimizer at
http://www.eecg.toronto.edu/~lemieux/sega/sega.html

http://193.215.128.3/freecore/ gives plans for building a programmer to
load designs into Altera FPGAs.


While I not sure how well-optimized the output from such software is, it
is interesting to note that someone with relatively basic electronics and
computer programming experience could put together a massively parallel
key-cracker.






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