1994-08-26 - Re: DSPs

Header Data

From: Phil Karn <karn@unix.ka9q.ampr.org>
To: jdd@aiki.demon.co.uk
Message Hash: 29d7215e07efa71f1eb9f0655f22f673b42537a9e1c446aa25e6747c51de94f8
Message ID: <199408262009.NAA17046@unix.ka9q.ampr.org>
Reply To: <8050@aiki.demon.co.uk>
UTC Datetime: 1994-08-26 20:05:06 UTC
Raw Date: Fri, 26 Aug 94 13:05:06 PDT

Raw message

From: Phil Karn <karn@unix.ka9q.ampr.org>
Date: Fri, 26 Aug 94 13:05:06 PDT
To: jdd@aiki.demon.co.uk
Subject: Re: DSPs
In-Reply-To: <8050@aiki.demon.co.uk>
Message-ID: <199408262009.NAA17046@unix.ka9q.ampr.org>
MIME-Version: 1.0
Content-Type: text/plain

>This is somewhat different than the kind of fast multiplication you are
>looking for.

Yes, but even scalar multiplication is so much faster on a DSP than on
most general purpose CPUs that it seems like a definite win. The 486
takes from 13-42 clock cycles to perform a multiply, depending on the
operand sizes and number of significant bits in the multiplier. Even
if you couldn't keep the pipeline full on a chip like the PowerPC, you'd
still be well ahead.

But then I hear people say that it's not the multiplication that slows
down modular exponentiation, it's the modular reduction.