From: Jyri Poldre <jp@jep.pld.ttu.ee>
Date: Thu, 26 May 94 09:58:24 PDT
To: cypherpunks@toad.com
Subject: Learning to divide ( again )
In-Reply-To: <9405261517.AA01689@toad.com>
Message-ID: <Pine.3.07.9405261946.A10899-b100000@jep.pld.ttu.ee>
MIME-Version: 1.0
Content-Type: text/plain


RE every1.

Recently i became involved in project of designing semi-custom VLSI device 
for endecryption. The device uses variable length RSA for key exchange and
IDEA for data encryption. For pipelinig IDEA block we have to use 6
multipliers 16 bit ant that leaves us with 96 bit adder for RSA calculations.
( The chip should be reasonably cheap ). Otherwise the RSA speed would not
be so cruicial but we have to generate both keys in chip ( involves
physically random generator based on variable frequency being samled with
constant clock, VF generator is inside chip )  to guarantee absolute
secrecy - you cannot tell Secret component if you do not know it. To
generate keys we have to use Fermat test for primality and that takes
time. Although the RSA keys need not to be changed so very often it is
still important to keep the process running in 'normal' time limits.
So - I can use multiple operand adders ( meaning a+b+c+d with one 
carry-propagation time ) For RSA basic operation a*b mod Z  i have
decided to use radix4 modified Booth algoritm for multiply , but i am still
not sure about divide. Has any1 encountered similar problems? I would greatly
appreciate Feedback, cause i have to make up my mind in some weeks. 
 If you are interested in more details about the design, let me know. 
I would like it to be good product for use in different applications.
  
JP from PLDesign lab of Tallinn Technical University.