From: Adam Shostack <adam@bwh.harvard.edu>
Date: Fri, 19 Aug 94 14:16:43 PDT
To: cypherpunks@toad.com (Cypherpunks Mailing List)
Subject: Cray contract info
Message-ID: <199408191805.OAA03282@walker.bwh.harvard.edu>
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| From: HPCwire article-server <more@hpcwire.ans.net>
| Message-Id: <199408191753.AA16894@hpcwire.ans.net>
| To: adam@bwh.harvard.edu
| Subject: 4493 CRAY COMPUTER AWARDED CRAY-3/SSS DEVELOPMENT CONTRACT August 17
| 
| CRAY COMPUTER AWARDED CRAY-3/SSS DEVELOPMENT CONTRACT             August 17
| IN THE NEWS by Carol Cramer, Managing Editor                      HPCwire
| =============================================================================
| 
|   Colorado Springs, Colo. -- A joint development contract between Cray
| Computer Corporation and the National Security Agency (NSA), valued at up
| to $9.2 million, is slated to produce a CRAY-3/Super Scalable System (SSS).
| 
|   Under the terms of the contract, Cray Computer Corporation will be paid up
| to $4.2 million for development costs, and the Government will provide
| approximately $400 thousand in software consulting services. The company is
| responsible for the balance of the development costs. In addition, it will
| have rights to use certain Government technologies.
| 
|   The CRAY-3/SSS will be a hybrid high performance system that will offer
| vector parallel processing, scalable parallel processing and the
| combination of both.
| 
|   "NSA selected Cray Computer Corp. to develop the CRAY-3/Super Scalable
| System because of its advanced technologies and the CRAY-3 architecture,"
| stated George Cotter, chief scientist for the NSA. "This is an important
| initiative of the Federal High Performance Computing and Communications
| (HPCC) program."
| 
|   Chuck Breckenridge, executive vice president for Cray Computer
| Corporation, noted, "The CRAY-3/SSS will provide unparalleled performance
| for many promising applications. We are pleased to participate in this
| transfer of government technology and we are eager to help potential
| customers explore and develop appropriate applications."
| 
|   Based on a September 1993 feasibility study, this development recommends a
| hybrid supercomputer composed of a CRAY-3 and a large number of Processor-In-
| Memory (PIM) chips, developed by the Supercomputing Research Center (SRC:
| Institute for Defense Analyses). The SRC will provide significant technical
| assistance in both the software and hardware aspects of the system.
| 
|   The Government's technology transfer program is intended to maintain the
| country's technology leadership position by providing a cost sharing
| arrangement for development and commercialization of advanced Government
| technologies.
| 
|   The high performance system will consist of a dual processor 256 million
| word CRAY-3 and a 512,000 processor 128 million byte Single Instruction-
| Multiple Data (SIMD) array. This CRAY-3/Super Scalable System will provide
| high-performance vector parallel processing, scalable parallel processing
| and the combination of both in a hybrid mode featuring extremely high
| bandwidth between the PIM processor array and the CRAY-3. SIMD arrays of 1
| million processors are expected to be available using the current version
| of the PIM chip once this development project is completed.
| 
|   The scalable array will connect to the CRAY-3 memory interface and will
| be addressable as standard memory to facilitate use of the SIMD array with
| minimal delays for data transfer. The PIM chip, containing 64 single bit
| processors and 128K bits of memory, was developed by the Supercomputing
| Research Center for NSA, and tested on a Sun/SPARC workstation with a
| parallel version of the C language.
| 
|   The PIM chips will be packaged by Cray utilizing its advanced multiple
| chip module (MCM) packaging technology that allows the CRAY-3 to operate
| with a record breaking 2.08 nanosecond clock rate. The PIM chips are
| manufactured by National Semiconductor Corporation. The CRAY-3/SSS is
| expected to be demonstrated in the first quarter of 1995. After this
| initial demonstration, interested parties will be invited to try out other
| applications.
| 
|   The CRAY-3 memory interface bandwidth will allow the application specific
| SIMD array to provide dramatic performance improvements over existing
| architectures for bit and image processing, pattern recognition, signal
| processing, and sophisticated graphics applications. A notable strength of
| the SIMD processor array is variable precision floating point for those
| frequently occurring applications requiring less (and sometimes more) than
| the standard 64 bit IEEE floating point arithmetic. A substantial
| applications base is available for the CRAY-3, and Cray Computer Corporation
| is committed to working closely with customers to develop traditional high
| performance vector and scalable applications.
| 
|   For suitable applications, the SIMD processor array option offers up to
| 32 Trillion Bit Operations per Second and provides price/performance
| unavailable today on any other high performance platform. The CRAY-3 system
| with the SSS option will be offered as an application specific product and
| will be well positioned in the evolving supercomputer marketplace.
| 
|   Seymour Cray stated, "The CRAY-3/SSS development project leverages the
| company's existing technologies and accelerates our program to develop
| parallel architectures and software to reach the TeraFLOPS performance
| level. I see a strong SIMD architectural component as crucial to a complete
| parallel supercomputer capability."
|
| *****************************************************************************
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