From: Remo Pini <rp@rpini.com>
Date: Thu, 25 Jul 1996 02:01:36 +0800
To: cypherpunks@toad.com
Subject: Re: Distributed DES crack
Message-ID: <9607241434.AA25033@srzts100.alcatel.ch>
MIME-Version: 1.0
Content-Type: text/plain


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To: cypherpunks@toad.com
Date: Wed Jul 24 16:31:44 1996

Has anyone thought about TI or Motorolas DSP-Eval-Boards (at 99$ a piece at 
40 MHz with optimized assembler they might easily outrun a PPro200)
Don't look at me that way, I know only little about DSP-Programming.

By the way, using FPGA's (as suggested earlier) at around 100 MHz should be
extremely fast (after all, on one 100000 Gate FPGA, one should be able to 
do lot of parallel things at one clock cycle -> test several keys at 
once...).
I estimate, that at reasonable cost (lets say, <$500) you should be able to 
put enough FPGAs on a board to do enough keys in parallel to equal 1 key 
per cycle, i.e. 1e8 keys/sec.
That would amount to: 7.2e8 secs ->8340 days
If you build 100 such machines you win in 3 months (without any of the 
mentioned optimisations (2e55 instead of 2e56, etc.)


- --------< fate favors the prepared mind >--------
Remo Pini                            rp@rpini.com
PGP:  http://www.rpini.com/remopini/rpcrypto.html
- ------< words are what reality is made of >------
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