From: "A. Padgett Peterson P.E. Information Security" <PADGETT@hobbes.orl.mmc.com>
Date: Mon, 3 Feb 1997 17:41:11 -0800 (PST)
To: eb@comsec.com
Subject: Re: RC5-12/32/5 contest solved
Message-ID: <199702040141.RAA09191@toad.com>
MIME-Version: 1.0
Content-Type: text/plain


>I received a nice flyer in the mail the other day from "Chip Express"
>(www.chipexpress.com, 800-95-CHIPX). They are offering Laser
>Programmed Gate Arrays.  It appears to be a reasonable way to get some
>Wiener chips built.  As I recall, the Wiener design required about
>23,000 gates.  Their blurb had the following table in in:

>  FPGA Gates  ASIC Gates  500 Units  1000 Units  5000 Units
>    40,000      20,000      $77        $45         $10
>   Not Avail   200,000     $176       $150         $82

First I can buy a 486DX-66 (with fan) for $37, but to make it into a PC 
takes just a wee bit more. Second, there is a world of difference in speed
between a Field Programmable Gate Array and an Application Specific
Integrated Circuit. The second is much faster (have heard of up to 200 Mhz)
but doubt that you can get there with a laser (probably where the 50 Mhz
figure comes from). I suspect you will need to have a mask made first - that 
is where the real money goes. However lets consider that you are really lucky 
and the first mask works and you get 100% yield (good chips).

Next you need a backplane with an input mechanism to prime each of those
chips with the text to break (will assume you have built in the 
initialization sequences for each chip). Then you need a path to provide
the KPT to the XOR at the output, powersupply, RF shielding, and a few 
other minor items (can probably use a PC for a front end).

Then, you need a way to report success but that is trivial.

Finally, you need to hope that none of those 5000 chips experiences infant
mortality or that you have some scheme to detect if that happens and to
which chip (was there BITE in the design ?).

Personally, would design the 5,000 to provide possible answers (say 2^32)
as an initial step and then push that into a single MasPar or similar. Might
find out some interesting things that way while reducing the overall 
complexity.

Just some food for thought.
					Warmly,
						Padgett

ps couple of people last year were working with FPGAs, I corresponded
   with them briefly. Why not ask them how my "guesstimates" correlated
   with their experiments...